CMOS Amplifier Design NDSU , ECE 723 Prepared by : Mariam Hoseini Spring 2008

Analysis and design of a CMOS current reused cascaded distributed amplifier with optimum noise performance

In this paper, analysis, simulation and design of a distributed amplifier (DA) with 0.13µm CMOS technology in the frequency range of 3-40 GHz is presented. Gain cell is a current reused circuit which is optimum in gain, noise figure, bandwidth and also power dissipation. To improve the noise performance in the frequency range of interest, a T-matching low pass filter LC network which is utilize...

A new compensation technique for two-stage CMOS operational transconductance amplifiers

This paper presents a new compensation method for fully differential two-stage CMOS operational transconductance amplifiers (OTAs). It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for minimum settling time of the proposed compensation technique for a two-stage class A/AB OTA is described. To demonstrate ...

A 28-36 GHz Optimized CMOS Distributed Doherty Power Amplifier with A New Wideband Power Divider Structure

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier. Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency range of 26.5-40GHz. To design the power amplifier, first a power divider (PD) with a ver...

Analysis and Design of High Gain, and Low Power CMOS Distributed Amplifier Utilizing a Novel Gain-cell Based on Combining Inductively Peaking and Regulated Cascode Concepts

In this study an ultra-broad band, low-power, and high-gain CMOS Distributed Amplifier (CMOS-DA) utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created bycascading of inductively coupled common-source (CS) stage and Regulated Cascode Configuration (RGC).The proposed three-stage DA is simulated in 0.13 μm CMOS process. It achieves flat and high ...

A Survey on RF Design